The use of local buses has become increasingly popular in the personal computer industry. Local buses are buses used to connect the system's processor to high bandwidth I/O peripherals such as displays, disk drives, etc. One such local bus in widespread use today is the PCI local bus. Because the PCI local bus has gained widespread acceptance, the buffer of the invention will be illustrated for use with this bus. The invention is not limited, however, to a buffer for this or any other particular bus or for use with the specific voltages discussed below.
The PCI Local Bus Specification, Rev. 2.1s, dated Jun. 1, 1995 (hereinafter referred to as the "PCI Spec"), defines two signaling environments, a 5 volt signaling environment and a 3.3 volt signaling environment. 5 volt and 3.3 volt refer to the voltage of a logical "1" signal in the respective signaling environments. The PCI Spec dictates that the signal voltage be clamped to 3.3 volts in a 3.3 volt environment, but does not require this clamping function in a 5 volt environment. The PCI Spec also contemplates a "universal board" that is capable of detecting the signaling environment in use and adapting itself to that environment.
The PCI local bus signaling environments are not dependent upon the component technologies used. A "5 volt component" can be designed to work in a 3.3 volt environment; and a "3.3 volt component" can be designed to work in a 5 volt environment. Component technologies of both voltages may be present on a PCI local bus at the same time. The PCI Spec contemplates 5 volt tolerant 3.3 volt implementations of universal boards. A 5 volt tolerant, 3.3 volt universal board is one implemented with 3.3 volt components that can function in a 5 volt signaling environment or a mixed 5 and 3.3 volt signaling environment. "3 volt," and "3.3 volt" as used herein refer to a nominal 3.3 volt voltage level; "5 volt" refers to a nominal 5 volt voltage level. The term "bus" as used herein refers not only to a formal bus architecture, but to any signaling path between any two devices. The term "pad" as used herein refers to a terminal or other physical electrical connection to a bus or signaling path.
FIG. 1 illustrates a known 5 volt tolerant, 3.3 volt output buffer 14 for use in a universal board. The buffer 14 is connected to the bus at pad 10. The additional buffer circuitry 18 is the circuitry that handles driving the bus (sourcing and sinking current to assert logic 1's or 0's, respectively) with a signal received from a peripheral, receiving data from the bus to drive a peripheral, and isolating a peripheral from the bus. Implementations of additional buffer circuitry 18 are well known in the art and need not be further discussed here. The buffer 14 includes a substrate voltage control circuit 16 that sets the substrate voltage for the p-type transistors included in the additional buffer circuitry 18. Because the voltage seen at the pad 10 may be 5 volts, which is higher than VDD=3.3 volts in a 5 volt tolerant, 3.3 volt buffer, the control circuit 16 is necessary to ensure that the substrate of p-type transistors is set to the highest voltage present. Should the substrate of the p-type transistors not be connected to the highest voltage present, undesirable or unpredictable behavior of the buffer may result as the p-n junctions between the active areas and the substrate may become forward biased. The substrate of the p-type transistors is an N-type well, referred to herein as an N-well or N-well substrate.
FIG. 2 illustrates a known substrate voltage control circuit 16 for use in a 5 volt tolerant, 3 volt buffer. The control circuit 16 includes a first P-type transistor 22 and a second P-type transistor 24. The gate of the transistor 22 is connected through a resistor 28 to the pad 10. The gate of the transistor 24 is connected through a resistor 26 to the supply voltage (referred to herein as "VDD"), which is 3.3 volts, at node 20. Resistor 26, together with the transistors 22, 24, form an output stage 32 with the gate of the transistor 22 being controlled by the voltage at the pad 10. One side of the transistor 22 is also connected to VDD. The other side of the transistor 22 is connected to one side of the second output stage transistor 24. The remaining side of the second output stage transistor 24 is connected to the pad 10.
As used herein, a "side" of a transistor is a generic term that refers to either the source or the drain, i.e., the connections to the active areas of the transistor. The transistors discussed herein are MOSFETs, which are symmetrical such that the source and drain are reversible. Because the voltages seen by some transistors are such that a single side of a transistor may function as a source under some conditions and a drain under others, only the generic term "side" will be used herein.
Operation of the known control circuit 16 in the presence of different signaling environments will now be described. In a 5 volt signaling environment, when the pad 10 is driven to a logic 1, nominally 5 volts, the transistor 22 will turn off, but transistor 24 will turn on. Transistor 24 turns on even though the gate is connected to VDD=3.3 volts because the gate of the transistor becomes more than one VTP (where VTP refers to the threshold voltage of the p-type transistor) below the 5 volts on the side of the transistor that is connected to the pad 10. The result is that the N-well voltage node 30 will follow the pad 10 voltage when the pad 10 voltage exceeds VDD+VTP. The substrates of the transistors 22, 24 are also connected to the N-well voltage node 30 to protect these transistors from damage along with the p-type transistors that form part of the additional buffer circuitry 18.
When the pad 10 is driven to logic 0 (nominally 0 volts), the transistor 22 is turned on and the transistor 24 is off. The result is that the N-well voltage node 30 is at VDD=3.3 volts. This is acceptable even in a 5 volt environment because VDD=3.3 volts will be the highest voltage present when the pad 10 is at a low voltage corresponding to logic 0.
In the 3.3 volt signaling environment, the transistor 24 is normally off because the gate is connected to VDD and the pad 10 is normally below VDD+VTP. Therefore, when the pad 10 is driven low, the transistor 22 will turn on and the N-well voltage node 30 will be at VDD=3.3 volts. However, when the pad 10 is driven high, both transistors 22 and 24 turn off. The result is that first, the signal voltage at the pad 10 is no longer clamped by the connection through the transistor 22 to the supply voltage VDD=3.3 volts; and second, the N-well voltage node 30 is allowed to float. This is in contravention to the PCI spec, which dictates that the signal voltage be clamped to 3.3 volts in the 3.3 volt signaling environment.
What is needed is a configurable substrate voltage control circuit that will reliably bias the N-well substrate of p-type transistors to the more positive voltage of either the supply voltage or the data on the bus under all operating conditions on the bus while providing the appropriate clamping function.